1. Field of the Invention
The present invention relates to circuit design and, more particularly to a method for designing an inverter circuit that offers fault-tolerance.
2. Description of the Prior Art
As far as a common circuit design is concerned, the inverter circuit design is not only widely applied in circuit designing, but is also an indispensable basic circuit design that is widely used. The FIG. 1a and FIG. 1b respectively show the block diagram and circuit diagram of an inverter. When the inverter is applied in a digital-logic circuit design, it is used to invert the signal, as the input point A and the output point B are shown in FIG. 1b. With the input signal of point A being xe2x80x9c1xe2x80x9d, point B outputs an inverted signal xe2x80x9c0xe2x80x9d. In contrast, when the input signal of point A being xe2x80x9c0xe2x80x9d, point B output is an inverted signal xe2x80x9c1xe2x80x9d.
The FIG. 1c which shows the inverter circuit layout diagram in semi-conductor fabrication, and FIG. 1d is the cross-sectional view from the line L-Lxe2x80x2 of the FIG. 1c. With the advancement of the semi-conductor fabrication and requirement of the density on a chip, thus the capacity of the transistors on an integrated circuit are increased, however, this means that the density of the circuit layout on an integrated circuit also raises. The input point 100 connects to the first signal wiring 104 through the first contact via 102. The second signal wiring 106 on the same layer is used to connect the source/drain implanting area 112A of the P-type transistor 112 and the source/drain implanting area 114A of the N-type transistor 114, and conducting the signal to the output point 110 through the second contact plug 108. It can be seen from the FIG. 1c and FIG. 1d that in the conventional inverter circuit layout, the first signal wiring 104 and the second signal wiring 106 are on the same metal layer, and the space S1 between the first signal wiring 104 and the second signal wiring 106 is the nearest place among the these wires, therefore, where is the place to a short circuit occurring during producing, and once if there is a short or open among the circuit, the function of whole circuit will become abnormal.
Accordingly, during the fabrication in a foundry, if there""s a problem with any wires or transistors of an inverter on a chip, the inverter cannot operate normally, and this affects the function of the whole chip. The influences by such defects are from the test yield before shipping to the reliability and the stability of whole system after the chip is used inside. That is to say, during the fabrication in a foundry, it""s easy to create flaws in the conventional circuit design, signal errors during testing, and even serious mistakes in the whole chip or system.
Concerning the defects that occur from the conventional inverter circuit design method in the background of the invention. In order to solve the disadvantages of the conventional inverter circuit, the present invention provides a method for designing fault-tolerant inverter circuit.
The object of the present invention is to provide a fault-tolerant inverter circuit.
Another object of the present invention is to improve the testing yield of the chip that contains the fault-tolerant inverter circuit of the present invention.
And still yet another object of the invention is to improve the reliability of a system that contains the fault-tolerant inverter circuit of the present invention.
According to the foregoing objects, the present invention provides a fault-tolerant inverter circuit, comprising: a signal inputting point and it is used to receive an inputting signal. A first inverter with an inputting end and an outputting end, and it is used to invert a signal from its inputting end to its outputting end, the inputting end of said first inverter connects to said signal inputting point. A second inverter with an inputting end and an outputting end is also used to invert a signal from its inputting end to its outputting end. The inputting end of said second inverter connects to the outputting end of said first inverter. A third inverter with an inputting end and an outputting end is used to invert a signal from its inputting end to its outputting end. The inputting end of said third inverter connects to the outputting end of said second inverter. A signal outputting pointconnects to the outputting end of said third inverter. A first conducting wire, the two ends of said first conducting wire connect to the said signal inputting point and the inputting end of said third inverter respectively. A second conducting wire, the two ends of the said second conducting wire connects to the outputting end of the said first inverter and said signal outputting point.
Accordingly, the fault-tolerant inverter of the present invention provides a fault-tolerance capability when any conducting wiring or any transistor is open, and even holds 50% of the fault-tolerance when any one transistor shorts. The invention also discloses that increasing the space in a specific location on the semiconductor-wiring layout to avoid a short from occurring.